Arrangement for and method of concurrent quadrature downconversion input sampling of a bandpass signal

ABSTRACT

An arrangement for generating a digital, downconverted complex baseband signal from a bandpass signal comprises a signal source for providing first and second clock signals at first and second clocking rates, respectively. The first clocking rate is at four times the expected center frequency of the bandpass signal, and the second clocking rate is at an exact subharmonic frequency of the bandpass frequency. The bandpass signal is sampled by a composite sampling event of two sampling pulses which occur once during each period of the second clocking signals and which are time-spaced from each other by the inverse of the first clocking rate. The complex baseband samples are ready as an A/D converter output, with no requirement for DSP processing to complete the downconversion to zero-IF.

BACKGROUND OF THE INVENTION

The invention relates generally to radio frequency receivers, and moreparticularly to circuits for sampling and converting received bandpasssignals to numerically quantified equivalents.

Sampling circuits, consequently, constitute interfaces between front-endanalog signal stages and back-end digital signal processor stages ofstate-of-the-art radio receivers. Digital Signal Processor (DSP)operations have become essential to modern radios, especially inimplementing modem functions of these radios. Radio receivers which usedigital signal processing techniques include those that use digitalmodulations, like PSK, as well as those that use analog modulations,like AM and FM. Until recently, all modem functions were performed byanalog circuitry.

VLSI technology and the deployment of communications satellites haveconcurrently spawned a rather rapid development of digital radiocommunications technology. Digital communications technology includesdigital information encoding or modulation, and conversely, decoding ordemodulation, of carrier frequencies with signalling techniques known,among others, as phase shift keyed (PSK) or differential phase shiftkeyed (DPSK) signalling.

The basic processing techniques to convert an RF analog signal receivedat an antenna, through frequency downconversion, to a digital basebandsignal are generally well understood and used. However, the techniquesused in the existing art for downconversion and sampling functionsgenerally demand comparatively costly components. In order for digitalcommunications to penetrate large consumer market segments, as would bedesirable for mobile satellite and digital cellular services,innovations in the radio art are required not only to improveperformance, as has been the trend in the past, but also to reduce thecost of radios.

It is therefore highly desirable to implement known signal digitizationand down conversion processes in more economical and more readilymanufacturable apparatus than has been provided by the complex prior artapparatus and methods.

SUMMARY OF THE INVENTION

It is therefore an object of the invention to provide a simple andefficient arrangement for generating complex baseband samples of abandpass signal.

It is a further object of the invention to generate through a digitalcircuit, separate and distinct from a DSP, a digital, zero-IF, complexbaseband equivalent of a bandpass signal.

It is another object of the invention to perform complex basebandsampling of a bandpass signal, using a single A/D converter, and withoutusing a digital signal processor for performing any of the operationsnecessary for generating a digital, zero-IF, complex baseband equivalentof the sampled bandpass signal.

It is yet a further object of the invention to provide an arrangementfor, and method of, concurrent quadrature downconversion and inputsampling of a bandpass signal.

In accordance with the invention, an arrangement for generating adigital, downconverted complex baseband signal from a bandpass signalcomprises a signal source for providing first and second timing signals,or clock signals, at first and second clocking rates, respectively. Thefirst clocking rate is at four times the expected nominal, or center,frequency of the bandpass signal, and the clocking rate of the secondclocking signal is at a subharmonic frequency of the nominal bandpassfrequency. The bandpass signal is sampled twice at the first clockingrate during each clocking period of the second clock signals. Asubharmonic frequency is any frequency which, when quantitativelyexpressed and divided into the quantitatively stated nominal frequencyof the bandpass signal, yields an integer.

BRIEF DESCRIPTION OF THE DRAWINGS

The Detailed Description of the Invention follows a Discussion ofExisting Art Related to the Invention, all described for a betterunderstanding of the invention in reference to the accompanying figuresof drawing wherein:

FIGS. 1 through 6 refer to illustrations relating to the discussion ofthe prior art; and

FIGS. 7 through 12 refer to and illustrate features of the presentinvention; and particularly,

FIG. 1 shows a block diagram of a prior art signal downconversion andsampling technique.

FIGS. 2a-2g shows spectra in prior art downconversion and samplingoperations that are representative of the signal processing elementshown in FIG. 1.

FIG. 3 shows a sampling circuit which transfers analog functionsdescribed with respect to FIG. 1 to a digital signal processor.

FIG. 4 shows a simplified sampling circuit of the prior art.

FIG. 5 shows a prior art sampling and downconversion technique which hasbeen used in state-of-the-art digital radios.

FIGS. 6a-6f shows spectra in real prior art bandpass sampling.

FIG. 7 shows a timing diagram of a continuous waveform and a sequence ofcomposite timing signals in accordance with the invention;

FIG. 8 shows signal spectra pertaining to sub-Nyquist, subharmoniccomplex signal sampling in accordance herewith;

FIG. 9 is a block diagram showing a preferred sampling circuit assemblyincluding features of the present invention;

FIG. 10 shows details of interfacing logic circuits of the preferredsampling circuit assembly shown in FIG. 9;

FIG. 11 is a timing diagram pertaining to the operation of the samplingcircuit of FIG. 9; and

FIG. 12 is a block diagram showing contemplated modifications asalternate embodiments of the preferred sampling circuit assembly shownin FIG. 9.

DISCUSSION OF EXISTING ART RELATED TO THE INVENTION

Digital processing of analog signals implies prior time sampling andamplitude quantization of the analog signals to generate a digitalequivalent of the analog signals. The digital equivalent of the analogsignals may then be transferred to a Digital Signal Processor (DSP) tobe processed. According to state-of-the-art digital techniques forextracting intelligent information from a signal, various techniqueshave been used which are now briefly described.

It is well known that a complex baseband representation of a carriersignal bears the same information about the carrier as its analyticalsignal, i.e., there is no useful information in the value of the IFitself. The "baseband" representation refers to an equivalent analyticalrepresentation of an IF signal at 0 Hz. The term "complex" denotes thatboth an In-phase or "I" component and a quadrature (90 degree phaseshift) or "Q" component of the signal are present, hence, the signal iscomplex when it has both I and Q components. It is known and understoodin the art that many, if not most, DSP operations on a digitized signalmay be more efficiently performed on a complex baseband signal than whenthe signal is in a real form. Consequently, such a digitized complexbaseband signal representation is desirably made available to a DSPprior to the execution of algorithms intended to extract information,such as encoded data, from the signal. Alternatively, DSP algorithms maybe used to perform, or complete, the conversion from real to complexbaseband form, loading the DSP with ancillary pre-processor operations.

FIG. 1 shows a block diagram of a traditional signal downconversion andsampling technique. In a conventional analog circuit 10, an IF signal isapplied via a branching node 11 to respective multiplying mixers 12 and14. At the mixers 12 and 14, the IF signal is multiplied by respectivequadrature local oscillator signals, cos(ω_(IF) t) 16 and -sin(ω_(IF) t)17, both at a frequency which is identical to the IF frequency, but at a90 degree relative phase relationship. The resulting I and Q signals,after passing through respective lowpass filters 18 and 19, are appliedto two low speed or "slow", analog to digital (A/D) converters 20 and21, respectively. Sampling the I and Q signals with the two A/Dconverters 20 and 21 yields a complex baseband signal in thediscrete-time domain. Downconverted and digitized complex baseband (Iand Q) signals are transferred from the analog and digital samplingcircuit 10 via a digital data bus 24 to a digital signal processor (DSP)25 for further processing operations.

FIGS. 2a-2g show spectra in the conventional down conversion andsampling operations that are representative of the signal processingelements shown in FIG. 1. FIG. 2a represents a real, as opposed to acomplex, signal spectrum of a typical IF signal. As is well known in theart, the real signal spectrum characteristically displays an evensymmetry about a baseband 0 Hz frequency axis, having an exact mirrorimage of a positive IF spectral component at the corresponding negativeIF frequency. FIGS. 2b and 2c show the spectra of the I and Q localoscillator signals, respectively, as generated by the local oscillators16 and 17 (see FIG. 1). It is well understood in the art that continuouswave signals, such as the respective sine and cosine waveforms, arerepresented by impulse functions in the frequency domain.

In reference to FIG. 1 and FIGS. 2d and 2e, the trace in FIG. 2d depictsthe spectrum of the output signal of the I-mixer 12 which multiplies theIF and the function cos(ω_(IF) t) with each other. FIG. 2e shows thetrace which represents the output of the Q-mixer 14, premultiplied by(j). Mathematical operations on complex numbers with real and imaginaryterms, wherein (j) is the square root of (-1), are readily performed bya DSP, as is well understood in the art. FIGS. 2d and 2e show a symbol(*) which is used to indicate convolution in the frequency domain,resulting in the respective spectra. Correspondence of convolution inthe frequency domain and multiplication in the time domain is a wellknown fact in communications theory. Since a complex baseband signal issynonymous with the sum of I and jQ components of a signal downconvertedto a zero center frequency, the summing of the spectra shown in FIGS. 2dand 2e results in the spectrum of the complex baseband equivalent of theIF signal. FIG. 2f represents a complex baseband spectrum as a sum ofthe spectra shown in FIGS. 2d and 2e. The summation cancels out thecontribution of the negative frequency component of Y(ω) while enhancingthe contribution of the corresponding positive frequency component,resulting in an asymmetrical baseband spectrum which is possible onlywhen the time-domain signal is complex.

Sampling the complex baseband signal with the two A/D converters 20 and21, as shown in FIG. 1 produces the desired spectrum shown in FIG. 2g.The spectrum shown in FIG. 2g is simply the repetition, at the samplingrate, of the baseband spectrum shown in FIG. 2f. The digitized signalsof FIG. 2f are the desired starting signals from which information cannow be extracted by further processing operations of the DSP 25. Thedescribed signal sampling process is used in various state-of-the-artdigital radios. Recognized disadvantages of the sampling circuit 10 arethat a comparatively large number of discrete analog components arecalled for. Moreover, for the sampling circuit 10 to functionsatisfactorily, all components thereof are subject to stringent gain andphase-shift matching requirements.

The disadvantages of the traditional sampling technique described withrespect to FIG. 1 are well recognized and, more recently, other samplingtechniques have become known in the art. FIG. 3 shows a sampling circuit44 which transfers the analog functions described with respect to FIG. 1to a digital signal processor 45 (DSP) to be performed as digital signalprocessing functions by the DSP 45. As shown in FIG. 3, an IF signal isapplied via an input node 46 to first and second A/D converters 47 and48. Sampled outputs of the first and second A/D converters 47 and 48 arefurther processed within the DSP 45. All signals within the DSP 45 arein a discrete-time domain. Digitized representations of the cos(ω_(IF)t) and the sin(ω_(IF) t) local oscillator signals (49 and 50,respectively), representable as impulse signals of a magnitude of (-1)and (1), are applied to respective digital I-mixer and Q-mixer functions51 and 52. Output signals pass through respective digital lowpass I andQ filter functions 53 and 54 to yield digitized complex basebandsignals, as represented by I and Q. The resulting digital downconversionfunction has the disadvantage of loading the DSP 45 with functions thatare ancillary to the core functions as, for example, signaldemodulation. As a consequence, a greater processing speed and memorybecome necessary. A greater processing speed and memory may be obtainedfrom a more complex and, hence, more costly DSP 45, or by using morethan a single DSP.

FIG. 4 shows further prior art, which is a simplification of the priorart depicted in FIG. 3. The simplification lies in the use of a singleA/D converter 56 which samples the IF signal at four times the nominalIF (4·IF). The 4·IF sampling rate is twice that of the normally requiredminimum sampling rate known as the Nyquist rate. By using the 4·IFsampling rate, the sampled result produces alternate In-phase andQuadrature component samples of the sampled signal. The digital samplesof the IF signal are now processed further by a digital signal processor57 or, more generally, as a digital signal processing function by one ormore digital signal processors, designated generally by the numeral 57.The sampled values are processed through a digital de-multiplexerfunction 58 which is clocked at the 2IF rate, or one-half of the initialsampling rate, such that sampled values are sent alternately to anI-mixer function and to a Q-mixer function 59 and 61, respectively. TheI-mixer and Q-mixer functions are, again as the sampling and downconversion circuit in FIG. 3, digital functions which would beimplemented by the digital signal processor function 57. At the I-mixerand the Q-mixer the demultiplexed I and Q components of the sampled IFare multiplied by respective cos(ω_(LO) t) and sin(ω_(LO) t) signals atthe local oscillator frequency. The functions cos(ω_(LO) t) andsin(ω_(LO) t) may be represented simply by their sampled values of (+1)and (-1). The digital mixer output signals are, as described withrespect to FIG. 3, passed through respective digital lowpass filters 62and 63, yielding the complex baseband signal represented by I and Qwhich may now be further processed by the digital signal processingfunction 57. As with respect to the sampling and down conversiontechnique described with respect to FIG. 3, the described sampling anddown conversion technique depicted in FIG. 4 tends to further load thedigital processor domain with substantial ancillary operations,increasing the DSP cost even further.

FIG. 5 shows a recent prior art sampling and downconversion techniquewhich has been used in state-of-the-art digital radios. The techniqueillustrated in FIG. 5 is unrelated to the sampling and downconversionapproaches described with respect to FIGS. 3 and 4. Similarly to theearlier described technique shown in FIG. 4, FIG. 5 depicts an IF signalbeing sampled by sampled as a real signal by a single A/D converter 65.As in the prior arrangements described with respect to FIGS. 3 and 4,the functions of obtaining the complex baseband form of the sampledsignal are shifted into the domain of digital signal processing,designated by a digital signal processing function block 66, which mayrepresent one or more digital signal processors 66. FIGS. 6a through 6fshow spectra in real bandpass sampling and, in further reference to FIG.5, illustrate this latter known example of prior-art sampling and downconversion of an IF signal to a complex baseband signal. The latterexample shows that what is known in the art as aliasing can be used as atechnique for down conversion of a signal provided a proper samplingrate is chosen which avoids overlap of aliased spectra. Avoidance ofspectral overlap is possible with bandpass signals and permits the A/Dconverter 65 to be used as a digital mixer 65.

FIG. 6a shows a real IF signal spectrum Y(ω) having a center frequencyof 450 kHz and a (stop) bandwidth of 6 kHz. Sampling the signal at afrequency of 12.081 kHz (see FIG. 6b) creates a component at audiofrequency (spectrum occupancy of 0 to 6 kHz), with a center frequency of3 kHz, as shown in FIG. 6c. This result is no different than a signalobtained by mixing the IF signal with a real local oscillator signal of447 kHz (which is approximately equivalent to a 37th harmonic of 12.081kHz), and which is subsequently lowpass filtered to a 6 kHz bandwidthand then sampled at 12.081 kHz. It must be noted in reference to FIG. 6cthat the signal has not been downconverted to true baseband (centerfrequency of 0 Hz) but to a low audio IF of 3 kHz. The signal cannot betranslated to a lower center frequency without causing spectral overlapwith the negative frequency component (image) of the real IF spectrum.Further digital processing of the sampled real, audio-IF signal withinthe digital signal processing function 66 yields the desired complexbaseband form of the signal. The further processing steps ancillary tothe DSP core function are as follows.

A well known digital signal processing operation, referred to in the artas a Hilbert transform 67 (see FIG. 5), suppresses thenegative-frequency spectrum (0 to -6 kHz) of the baseband componentshown in FIG. 6c, as well as the aliased versions of the (0 to -6 kHz)spectrum. The result of the spectra after the Hilbert transform 67 isshown in FIG. 6d. Time decimation by a factor of two, identified bynumeral 68, yields the spectra shown in FIG. 6e, packing the spectrawith a 6 kHz (6.04 kHz to be exact) repetition rate. A complexdownconversion function 69 ultimately yields the desired complexbaseband signal as shown in FIG. 6f. The complex baseband signal is thensubjected to further processing shown as 70, such as the core functionof digital signal processing, including typically demodulation of data.The increased complexity of digital processing over and above thatrequired for signal demodulation is well demonstrated by the abovedescription.

DETAILED DESCRIPTION OF THE INVENTION

In contrast to the known examples of the previously described prior art,the present invention is described in reference to FIGS. 7 through 11,wherein FIG. 7 shows an immediate distinction over the described knownart.

As a preferred embodiment of the present invention, FIG. 7 shows asimple timing diagram of a bandpass waveform, such as a 450 kHz IFsignal having a period of 1/IF or 1/450 kHz, and a bandwidth that issmall relative to 450 kHz. The signal is being sampled at a lowsubharmonic rate. A subharmonic rate, as the term is used herein,defines a rate which is an exact submultiple of the sampled signal.Thus, a rate of 6 kHz, for example, divided into the IF of 450 kHz,yields seventy-five, an integer, making 6 kHz a subharmonic of 450 kHz.Sub-Nyquist sampling was used in the prior art example described withrespect to FIGS. 5 and 6. Subharmonic sampling according to the priorart processes would have led to spectral overlap and, hence, signaldistortion. Thus, the prior art did not and could not have used asubharmonic sampling rate, as in the present invention. A furtherdistinction over prior sampling techniques become apparent bycharacteristic double sampling-pulse clusters, with an intra-clustertime spacing that is an inverse of four times the nominal IF, i.e., aphase-quadrature sampling rate, which corresponds to 1.8 MHz in therepresentative, preferred example. Significantly, the double-pulseclusters, though timed to yield an In-phase component (I) and aquadrature component (Q) of the sampled signal, occur as a discrete,composite single event during each sub-Nyquist, subharmonic samplingperiod. The sampling sequence, according to the invention, consequently,is characterized by a non-uniform time sampling rate wherein timespacing of sampling pulses alternates or switches betweenphase-quadrature spacing and relatively much greater time spacing, asdetermined by the exact subharmonic sampling frequency of the IF atwhich the sampling events occur. Referred to herein as a compositesampling process, the process uses a double-pulsed sampling event oroperation, with two sampling pulses at phase-quadrature time-spacing.Moreover, a single set of two phase-quadrature sampling pulses occursonly once during each composite sampling period, with the samplingperiod being chosen to be a sub-Nyquist and an exact subharmonic of thesampled bandpass signal. The composite and complex, sub-Nyquist andsubharmonic sampling directly yields the desired complex basebandsamples without further need for digital processing.

Spectra pertaining to composite, sub-Nyquist and subharmonic complexsampling are illustrated in FIGS. 8a-8f. Though not essential forunderstanding the embodiments of the present invention, the mathematicalconsiderations below are believed to be helpful in comprehending thetheory of operation of these embodiments.

It is to be realized that a complex repetitive sampling pulse, s(t), maybe represented by

    s(t)=Δ(t-nT)+jΔ(t-1/(4·IF)-nT)

where,

Δ(t-τ) represents an impulse function occurring at time τ; and

T is the sampling period.

The complex pulse train s(t) is derived from the real sequence of dualpulses, illustrated in FIG. 7, by assigning the first pulse of a pair tothe I component and the second pulse to the Q component. That is

    Re{s(t)}=I(t)=Δ(t-nT)

    Im{s(t)}=Q(t)=Δ(t-1/(4·IF)-nT)

A representation of s(t) in the frequency domain is similar to that of areal sampling pulse, except for the complex amplitude, i.e. ##EQU1##

The expression for S(f) shown above follows from the time-delay rule ofFourier transforms:

    F{x(t-τ)}=F{x(t)}·exp(-jωτ).

The result of convolution between S(f) and the IF signal spectra areshown in FIGS. 8a through 8f, wherein FIG. 8a shows characteristicspectrum of a real bandpass signal Y(ω), in the described example thereferred-to IF signal. FIG. 8b shows the spectrum of I(t), the real partof s(t) while FIG. 8c shows the spectrum of Q(t), the imaginary part ofs(t). FIG. 8d represents the result of convolution between the IFspectrum, Y(ω), and the spectrum of I(t). FIG. 8e depicts theconvolution between Y(ω) and the spectrum of Q(t), premultiplied by (j)to form the complex spectrum. Thus, ##EQU2## where Z(ω) is the resultantcomplex baseband spectrum,

Y(ω) is the IF spectrum, and

F{.} designates a Fourier transform.

It is to be noted that convolution in the frequency domain between twofunctions is equivalent to reversal of the frequency axis of onefunction, followed by cross-correlation between the two functions. Sinceconvolution is known to be a linear process, the spectra of FIGS. 8d and8e are additive to obtain a resultant spectrum as shown in FIG. 8f. Inthe above-described arrangement for achieving phase quadrature throughtime delay, a phase error does occur, which is insignificant as long asthe ratio of the IF bandwidth divided by IF is significantly less thanone. The phase error is equal to (π/2)(B/IF), where B is thesingle-sided IF bandwidth, i.e., half the width of the IF passband. Thephase error creates an in-band interference image with an amplitude ofapproximately the sine of the phase error. Thus, for an IF signal of 450kHz and a passband of +/-3 kHz, a corresponding phase error at the bandedge of 3 kHz amounts to 0.6 degrees and a correspondingself-interference equals approximately 20 log sine of the phase error,or -40 dBc. Such a level of self-interference is considered acceptablein applications of low signal to noise ratios at a detection end. Mobiledata communications systems in general, and mobile satellitecommunications systems in particular, fall into the category of such lowsignal to noise ratio systems.

Referring now to FIG. 9 there is shown a block diagram of a preferredA/D converter circuit 83 for a sub-Nyquist, subharmonic complexdownconversion of a bandpass signal to baseband (0 Hz center frequency).The A/D converter circuit 83 uses timing signals from a local timingsignal source 84, which timing signals bear a relationship to anexpected nominal frequency of the bandpass signal to be operated on. Thelocal timing signal source 84 should be understood to be collectively asource of at least first and second clock signals at first and seconddistinct signal rates, as further described herein. It is well knownthat frequencies of received RF signals tend to vary from a nominalfrequency for any of a number of reasons, including, for example dopplershifts and local oscillator drifts. As was described above, frequencyvariations with respect to an expected nominal frequency of the bandpasssignal will be tolerable as long as the desired signal is within the IFpassband, i.e., has a frequency error less than +/-B Hz. A bandpasssignal which, in the described example, is referred to as a final IFsignal, is applied as an input signal via a signal input port to ananalog-to-digital converter or A/D converter 86. The A/D converter 86 isone referred to in the art as a "fast" A/D converter because itsperformance must be adequate for sampling at four times the IF. A firsttiming signal supplied by the local timing circuit 84 is a samplingclock signal for the A/D converter 86. The generated first timingsignals are time-spaced at intervals of an inverse of a signal rate offour times the IF (1/4·IF). In a specific example, of the IF signalhaving a frequency of 450 kHz, the sampling clock, applied to a timingport of the converter 86, generates periodic sampling pulses at a rateof 1.8 MHz. The 1.8 MHz pulse rate constitutes a quadrature samplingpulse rate for the 450 kHz IF signal as described with respect to FIG.7. As shown in FIG. 9, the 1.8 MHz timing signal further becomes theclock for a logic circuit 87, also referred to as glue logic 87. Asecond timing or clock signal supplied by the timing source 84, forcomplex sampling of the IF signal at a true subharmonic frequency, 6 kHzin the example, is also provided to the glue logic 87. Data sampled bythe A/D converter 86 at the 1.8 MHz clocking rate are applied via an8-bit bus 88 to two 8-bit signal latches which are respectivelydesignated as an I-latch 89 and a Q-latch 90. However, it is the gluelogic 87 which controls the events in time during which the sampledvalues are actually written to (locked into) the I-latch 89 and theQ-latch 90. In accordance herewith, the glue logic 87 issues only oneI-latch write command and only one Q-latch write command during eachtiming cycle, or timing period, of the 6 kHz clock, which timing cyclebecomes the actual sampling cycle for combined quadrature downconversionand input sampling in accordance herewith. Significantly, the Q-latchwrite command lags in time behind the I-latch write command by onetiming cycle or period of the 1.8 MHz clock signal, so that the gluelogic 87 generates a double-pulsed, complex sampling command which istime-spaced by intervals of an inverse of the sampling rate of 6 kHz(1/6 kHz). Because of the double sampling pulses, spaced in time by1/1.8 MHz, each composite, complex sampling period of 1/6 kHz secondsgenerates digital data for a complex baseband representation of the IFsignal. It is, consequently, the combination of only the glue logic 87and the I-latch 89 and Q-latch 90, which generates in a simple manner, atrue digital complex baseband representation of the IF signal, using thedigital samples generated by the A/D converter 86.

Although both I and Q signal components are channeled via the bus 88 toboth the I-latch 89 and the Q-latch 90, the write signals of thereferred-to glue logic 87 enable the I-latch 89 to latch in the In-phasesamples, while the Q-latch write signals, delayed by a (1/1.8)×10⁻⁶sec., latch in the quadrature samples. The I and Q samples latched intothe respective I-latch 89 and Q-latch 90 are then written via a 16-bitdata-out bus 91 (including 8 data bits from each of the latches 89 and90) to a digital signal processor 92 (DSP) at the subharmonic samplingrate of 6 kHz. A 6 kHz DSP interrupt signal by the glue logic 87 via asignal line 93 coupled to the DSP, causes the DSP 92 to read the sampleddata at the I and Q data latches 89 and 90. According to the described,preferred embodiment, the write to the Q-latch 90 and the interrupt tothe DSP 92 occur simultaneously. However, the DSP 92 has a finiteinterrupt service time which equates to a distinct response delay by theDSP 92. Therefore, the finite interrupt service time of the DSP 92ensures that the I and Q data are latched in the respective I-latch 89and the Q-latch 90 before the I and Q data are read by the DSP 92.

It should be realized that the described A/D converter circuit 83supplies the DSP with a true digital-complex-baseband equivalent of theIF signal. No further signal conversion operations are required by theDSP 92 prior to its core operations of acquiring and demodulating thereceived signal to extract received data or communications. Theoperations within the digital domain, in the present example the DSP 92,are therefore relieved of the processing-intensive steps of generatingthe downconverted digital complex baseband signal, as had been thepractice in certain prior art examples, as described above.

In reference to FIGS. 10 and 11, FIG. 10 depicts a preferred arrangementfor implementing the glue logic circuit 87, while FIG. 11 shows a timingdiagram of graphs "a" through "e" with timing sequences for latching theIn-phase and Quadrature sampling events and transferring the sampleddata to the DSP 92 (of FIG. 9). First and second D-type flip-flopcircuits 94 and 95 (U1 and U2, respectively) are both clocked atrespective clock ports (CLK) by the 1.8 MHz (4*IF) signal (graph a). The6 kHz signal (graph b) is applied to a D1 input port or terminal of thefirst flip-flop circuit 94, and the Q1 output port or terminal of thecircuit 94 is coupled to the D2 input data port or terminal of theflip-flop circuit 95. The rising edge of the Q1 output also representsthe write command (graph c) to the positive-edge triggered I-latch 95(shown in FIG. 9), which is delayed by a one timing period of the 1.8MHz clock with respect to 6 kHz timing signal (graph b). The Q2 outputis coupled as the write command (graph d) to the positive-edge triggeredQ-latch 95 (of FIG. 9), showing an added delay of one 1.8 MHz clockcycle, hence of 1/4 IF with respect to the Q1 write command (graph c).

During an operational sequence of the described A/D converter circuit 83(see FIG. 9), and more particularly the logic circuit 87 (see FIGS. 9and 10), Q1 goes positive on the first positive transition of the 1.8MHz clock after D1 goes positive. Q2 goes positive on the firsttransition of the 1.8 MHz clock signal after Q1 goes positive, as Q1 isconnected to D2. Both the I-latch 94 and the Q-latch 95 are positiveedge triggered, as mentioned above. An interrupt signal is generated atthe inverse Q2, or not-Q2, output port and applied at 96 to the digitalsignal processor 92, which is negative-edge triggered. The interruptrequest service time is sufficiently long to avoid any timing contentionbetween writing and reading the Q-latch 95.

Referring back to FIG. 9, it is to be realized that the disclosedcircuit 83 may be implemented either by discrete logic circuits, whereinthe A/D converter 86 is a separate device and the glue logic 87 iscomprised of various, separate glue logic chips, or by integrated logicfunctions, combining, for example, A/D and glue logic functions in asingle device 83. It is also possible for the DSP 92 and the convertercircuit or input sampling circuit 83 to be integrated into a singlemixed-signal Application Specific Integrated Circuit (ASIC), wherein thedescribed composite, complex sampling technique is expected tocontribute to a circuit simplification of a resulting ASIC.

It should be realized that the use of downconverted complex basebandsignals applies to many, if not most, digital processing techniques usedin digital radios, as well as in non-radio applications using digitalsignal processing. Prominent non-radio applications to which the presentinvention may advantageously apply are radar, direction finding andposition location, automotive applications and robotics. Thus, ofsignificance is the generation of the digital complex baseband signalrepresentation of a sampled analog signal in the manner and by thearrangements described herein, rather than the application of thedigital complex baseband signal to any one particular digital signalprocessor.

Keeping in mind that the downconverted complex baseband signal of thebandpass signal is obtained sampling with a composite, phase-quadraturedouble-pulse sampling event at a true subharmonic sampling rate of thefrequency of the bandpass signal, various modifications and alternativeimplementations within the scope of the invention come to mind. FIG. 12shows, for example, an alternative to the converter circuit 83 of FIG.9, according to which the A/D converter 86, instead of being coupled tocontinuous phase-quadrature timing signals, is driven by a glue logiccircuit 97. The glue logic circuit 97 is operated by the timing circuit84, the timing circuit 84 supplying first timing signals at aphase-quadrature rate and second timing signals at a true subharmonic ofthe input IF signal, shown as a clock rate of IF divided by an integer"n" (IF/n). In response, the glue logic 97 generates, as described abovewith respect to the glue logic 87, the described composite, complextiming sequence consisting of a phase-quadrature double-pulse burst oftiming signals at a true subharmonic rate (IF/n) of the IF signal. Thus,instead of being operated at a steady rate of phase-quadrature pulses atfour times the IF, as described with respect to FIG. 9, the A/Dconverter 86 would now sample in bursts, i.e., at a composite samplepulse rate with a single phase-quadrature or complex double-pulsesampling event or operation occurring at a selected subharmonic rate ofthe IF. The A/D converter 86 would take two samples in rapid succession(time-spaced at a phase-quadrature interval, i.e., 4·IF), then remainidle for the remainder of the subharmonic sampling period. The sampled,digital output from the A/D converter 86 appears simultaneously, asdescribed above with respect to FIG. 9, at both the I-latch 89 and theQ-latch 90, but concurs in time with the respective write commands tothe I-latch 89 and to the Q-latch 90. The I and Q data are,consequently, latched into the respective I-latch 89 and Q-latch 90 onoccurrence of the respective I-write and Q-write signals. The latcheddata are sampled by the DSP 92 at the subharmonic sampling rate inaccordance with an interrupt applied via the signal line 93.

The alternative embodiment in FIG. 12, of pulsing the A/D converter 86with at a composite double pulse rate of four times the bandpass signalfrequency (4·IF) but at the comparatively much slower subharmonic rateof second alternate example, suggests a further cost-savingsimplification, illustrated also with respect to FIG. 12. Accordingly,the single A/D converter 86 is replaced by first and second A/Dconverters 98 and 99, respectively. The first A/D converter 98 is pulsedwith a sampling pulse being the first of the described double pulses viaan I-signal line 100, while the second A/D converter 99 is pulsed with asampling pulse being the second of the double pulses via a Q-signal line101 (In case of the single A/D converter 86, both of the double pulsesare applied to the same timing port of the A/D converter 86). The firstA/D converter 98 applies the sampled output solely to the I-latch 89 viadata bus 102, while the second A/D converter 99 applies the sampledoutput solely to the Q-latch 90 via data bus 103. Sampled data arewritten to the I and Q latches 89 and 90, as previously described, inresponse to respective I-write and Q-write signals from the glue logic97, which occur on completion of the respective I and Q samplingoperations, and are applied via respective write signal lines 104 and105. The interrupt signal applied via the interrupt signal line 93causes the DSP 92 to read the latched I and Q samples from therespective I and Q latches 89 and 90 via data bus 106. The use of 8-bitlatches for the I and Q data latches 89 and 90, and the use ofrespective 8- and 16-line data buses into the latches 89, 90 and intothe DSP 92, respectively, corresponds to a preferred word length for adigital representation of the sampled signal, and should be regarded asillustrative and not as limiting the scope of the invention. Though thefirst and second A/D converters 98 and 99 in the latter example may needto be matched in performance, a distinct advantage is obtained in thateach of the A/D converters 98 and 99 are now operated at thecomparatively slow sampling rate of IF/n, a subharmonic of the inputbandpass signal frequency, which allows slow and comparativelyinexpensive A/D converters to be selected to function effectively in thedescribed embodiment. The use of the slow sampling rate in each of theA/D converters 98 and 99 further implies sampling bandpass signals atcomparatively higher frequencies, opening the way to eliminating adownconversion stage of input frequencies.

As will be realized from the above detailed description, all of theembodiments therein are illustrative and are specific examples ofapparatus and methods pursuant to the invention. Various changes andmodification to the described apparatus may be made in view of the abovedescription without departing from the spirit and scope of the inventionwhich is defined by the claims below.

What is claimed is:
 1. A sampling circuit for concurrent quadraturedownconversion and input sampling of a bandpass signal comprising:meansfor generating first timing signals time-spaced by an inverse of a firsttiming signal rate of four times a center frequency of the bandpasssignal; means for generating second timing signals time-spaced by aninverse of a second timing signal rate, the second timing signal ratebeing a subharmonic rate of the center frequency of the bandpass signal;and means for sampling the bandpass signal at the second timing signalrate with a single set of composite, phase-quadrature double pulses, thedouble pulses being time-spaced by the inverse of the first timingsignal rate.
 2. The circuit according to claim 1, wherein the means forsampling the bandpass signal comprises:A/D converter means forgenerating digital samples of the bandpass signal in response tosampling pulses applied to the A/D converter means; a first data latch,coupled to the A/D converter means, for latching in the generateddigital samples of the bandpass signal in response to and at the time ofa first write command applied to the first data latch; a second datalatch, coupled to the A/D converter means, for latching in the generateddigital samples of the bandpass signal in response to and at the time ofa second write command applied to the second data latch; glue logicmeans, coupled to the means for generating first timing signals and tothe means for generating second timing signals, for generating acomposite timing sequence of first and second timing pulses time-spacedby the inverse of the first timing signal rate and repeated at a rate ofthe inverse of the second timing signal rate, and for generating andapplying first and second write commands to the first and second datalatches, respectively, the first and second write commands beingtime-spaced by the inverse of the first timing signal rate; and meansfor applying sampling pulses to the A/D converter means, the samplingpulses being time-spaced by the inverse of the first timing signal rate.3. The circuit according to claim 2, wherein the means for applyingsampling pulses comprises means for coupling the means for generatingfirst timing signals to the A/D converter means and the sampling pulsesare applied continuously.
 4. The circuit according to claim 2, whereinthe means for applying sampling pulses comprises means for coupling theglue logic means to the A/D converter means and the sampling pulsescomprise two pulses time-spaced by the inverse of the first timingsignal rate, the two pulses occurring as a composite sampling eventtime-spaced by the inverse of the second timing signal rate.
 5. Thecircuit according to claim 1, wherein the means for sampling thebandpass signal comprises:A/D converter means, coupled to the means forgenerating the first timing signals, for generating digital samples ofthe bandpass signal at the first timing signal rate; first and seconddata latches, coupled to the A/D converter means, for latching in thegenerated digital samples of the bandpass signal in response to and atthe time of a write command applied to the first and second datalatches, respectively; control means, coupled to the means forgenerating first timing signals and to the means for generating secondtiming signals, and further coupled to the first and second data latchesfor applying a first pulse of the set of double pulses as a first datalatch write command to the first data latch, and applying a second pulseof the set of double pulses as a second data latch write command to thesecond data latch.
 6. The circuit according to claim 5, wherein thefirst and second data latches are coupled to a digital signal processor,and wherein the control means further comprises means for generating alatch read control signal upon having applied the first and secondpulses of the set of double pulses to the respective first and seconddata latches, the latch read control signal being applied to the digitalsignal processor to cause the digital signal processor to read thedigital samples latched in the first and second data latches.
 7. Thecircuit according to claim 5, wherein the control means comprises firstand second D-type flip-flop circuits, a data port D1 of the first D-typeflip-flop circuit being coupled to the means for generating first timingsignals, an output port Q1 of the first flip-flop circuit being coupledto the first data latch and to an input data port D2 of the secondD-type flip-flop circuit, clocking ports of the first and the secondD-type flip-flop circuits being coupled to the means for generatingsecond timing signals, an output port D2 of the second flip-flop circuitbeing coupled to the second data latch, and a not-Q2 output port of thesecond flip-flop circuit being coupled to an interrupt port of a digitalsignal processor.
 8. A method of generating a digital, downconvertedcomplex baseband signal from a bandpass signal of an expected centerfrequency comprising:generating first timing signals at a first rate offour times the frequency of the expected center frequency of thebandpass signal; generating second timing signals at a second rate of atrue subharmonic frequency of the expected center frequency of thebandpass signal; and sampling the bandpass signal at the second rate ofthe second timing signals and with a composite double pulse event havinga single occurrence of a first sampling pulse and a second samplingpulse time-spaced by an inverse of the first rate of the first timingsignals.
 9. The method according to claim 8, wherein the bandpass signalis an IF signal at an expected center frequency of 450 kHz, andwherein:generating first timing signals comprises generating timingsignals at a first rate of 1.8 MHz, and generating second timing signalscomprises generating timing signals at a second rate of 6 kHz.
 10. Themethod according to claim 8, wherein sampling the bandpass signalcomprises:sampling the bandpass signal by a single A/D convertersuccessively at the first rate of the first timing signals to generatesuccessive, digital samples of the bandpass signal at phase-quadratureintervals; applying the digital samples of the bandpass signal tosimultaneously to first and second data latches; and at timed intervalsin accordance with the second rate of the second timing signals and onoccurrence of the first sampling pulse, sending a write command to thefirst data latch and then, on occurrence of the second pulse, sending awrite command to the second data latch.
 11. The method according toclaim 10, further comprising sending a read command to a digital signalprocessor circuit upon the occurrence of the second sampling pulse. 12.The method according to claim 8, wherein sampling the bandpass signalcomprises:sampling the bandpass signal by a single A/D converter with adouble pulse time-spaced by the inverse of the first rate of the firsttiming signals to generate In-phase and Quadrature samples of thebandpass signal; repeating the double pulse sampling at the second rateof the second timing signals; and writing the In-phase samples to afirst data latch and the Quadrature samples to a second data latch. 13.The method according to claim 12, further comprising sending a readcommand to a digital signal processor circuit upon writing the In-phaseand Quadrature samples to the respective first and second data latches,to cause the digital signal processor circuit to read the respectivesamples as a digital, downconverted complex baseband signal of thebandpass signal.
 14. The method according to claim 8, wherein samplingthe bandpass signal comprises:sampling the bandpass signal by a firstA/D converter with a first pulse of a double pulse sampling event, thetwo pulses being time-spaced by the inverse of the first rate of thefirst timing signals, thereby generating an In-phase sample of thebandpass signal; sampling the bandpass signal by a second A/D converterwith a second pulse of the double pulse sampling event, therebygenerating a Quadrature sample of the bandpass signal; repeating thedouble pulse sampling event at the second rate of the second timingsignals; and writing generated In-phase samples to a first data latchand generated Quadrature samples to a second data latch.
 15. The methodaccording to claim 14, further comprising sending a read command to adigital signal processor circuit upon writing generated In-phase andQuadrature samples to the respective first and second data latches, tocause the digital signal processor circuit to read the respectivesamples as a digital, downconverted complex baseband signal of thebandpass signal.